A \(2\) V battery is connected across the points \(A\) and \(B\) as shown in the figure given below. Assuming that the resistance of each diode is zero in forward bias and infinity in reverse bias, the current supplied by the battery when its positive terminal is connected to \(A\) is:
1. | \(0.2\) A | 2. | \(0.4\) A |
3. | zero | 4. | \(0.1\) A |
In the circuit given below, if \(V(t)\) is the sinusoidal voltage source, then the voltage drop \(V_{AB}(t)\) across the resistance \(R\):
1. | is half-wave rectified. |
2. | is full-wave rectified. |
3. | has the same peak value in the positive and negative half-cycles. |
4. | has different peak values during the positive and negative half-cycles. |
1. \(0\) V
In a given circuit as shown the two input waveforms \(A\) and \(B\) are applied simultaneously. The resultant waveform \(Y\) is:
1. | 2. | ||
3. | 4. |
If the reverse bias in a junction diode is changed from \(5\) V to \(15\) V then the value of current changes from \(38~\mu \text{A}\) to \(88~\mu \text{A}\). The resistance of junction diode will be:
1. \(4\times10^{5}\)
2. \(3\times10^{5}\)
3. \(2\times10^{5}\)
4. \(10^{6}\)
The logic behind the 'NOR' gate is that it gives:
1. | High output when both the inputs are low. |
2. | Low output when both the inputs are low. |
3. | High output when both the inputs are high. |
4. | None of these |
Zener breakdown will occur if:
1. impurity level is low.
2. impurity level is high.
3. impurity is less on the \(\mathrm{n\text-}\)side.
4. impurity is less on the \(\mathrm{p\text-}\)side.
The energy band diagrams for semiconductor samples of silicon are as shown. We can assert that:
1. | Sample \(X\) is undoped while samples \(Y\) and \(Z\) have been doped with a third group and a fifth group impurity respectively. |
2. | Sample \(X\) is undoped while both samples \(Y\) and \(Z\) have been doped with a fifth group impurity. |
3. | Sample \(X\) has been doped with equal amounts of third and fifth group impurities while samples \(Y\) and \(Z\) are undoped. |
4. | Sample \(X\) is undoped while samples \(Y\) and \(Z\) have been doped with a fifth group and a third group impurity respectively. |
In the following circuit, the output \(Y\) for all possible inputs \(A\) and \(B\) is expressed by the truth table:
1. | A | B | Y | 2. | A | B | Y |
0 | 0 | 0 | 0 | 0 | 1 | ||
0 | 1 | 0 | 0 | 1 | 1 | ||
1 | 0 | 0 | 1 | 0 | 1 | ||
1 | 1 | 1 | 1 | 1 | 0 | ||
3. | 0 | 0 | 1 | 4. | 0 | 0 | 0 |
0 | 1 | 0 | 0 | 1 | 1 | ||
1 | 0 | 0 | 1 | 0 | 1 | ||
1 | 1 | 1 | 1 | 1 | 1 |
The circuit is equivalent to:
1. AND gate
2. NAND gate
3. NOR gate
4. OR gate