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Q. No.The given circuit has two ideal diodes connected as shown in the figure below. The current flowing through the resistance \(R_1\) will be:
1.
\(2.5\) A
2.
\(10.0\) A
3.
\(1.43\) A
4.
\(3.13\) A
Subtopic: Â PN junction |
 86%
From NCERT
NEET - 2016
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In the energy band diagram of a material shown below, the open circles and filled circles denote holes and electrons respectively. The material is a/an:
| 1. | \(\mathrm{p}\text-\)type semiconductor |
| 2. | insulator |
| 3. | metal |
| 4. | \(\mathrm{n}\text-\)type semiconductor |
Subtopic: Â Energy Band theory |
 74%
From NCERT
AIPMT - 2007
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A forward-biased diode is treated as:
| 1. | an open switch with infinite resistance. |
| 2. | a closed switch with a voltage drop of \(0\) V. |
| 3. | a closed switch in series with a battery with voltage of \(0.7\) V. |
| 4. | a closed switch in series with small resistance and a battery. |
Subtopic: Â PN junction |
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A half-wave rectifier voltage is fed to a load resistor. For which part of the cycle, the load current will flow?
| 1. | \(0^\circ-90^\circ\) | 2. | \(90^\circ-180^\circ\) |
| 3. | \(0^\circ-180^\circ\) | 4. | \(0^\circ-360^\circ\) |
Subtopic: Â Rectifier |
 54%
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If the input to the NOT gate is \(A\), its output is:
1. \(0\)
2. \(1\)
3. \(A\)
4. \(\overline{A}\)
Subtopic: Â Logic gates |
 82%
From NCERT
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The combination of gates shown below is equivalent to:
1. AND gate
2. XOR gate
3. NOR gate
4. NAND gate
Subtopic: Â Logic gates |
 68%
From NCERT
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In the given circuit, \(\mathrm{p\text-n}\) junction diodes \(D_1, D_2~\text{and}~D_3\) are ideal. For the following potential of \(A\) and \(B\), the correct increasing order of resistance between \(A\) and \(B\) will be:
ii. \(-5~\text{V}, -10~\text{V}\)
iii. \(-4~\text{V}, -12~\text{V}\)
1. (i) < (ii) < (iii)
2. (iii) < (ii) < (i)
3. (ii) = (iii) < (i)
4. (i) = (iii) < (ii)
ii. \(-5~\text{V}, -10~\text{V}\)
iii. \(-4~\text{V}, -12~\text{V}\)
1. (i) < (ii) < (iii)
2. (iii) < (ii) < (i)
3. (ii) = (iii) < (i)
4. (i) = (iii) < (ii)
Subtopic: Â PN junction |
 63%
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The depletion layer in the \(\mathrm{p\text-n}\) junction region is caused by:
| 1. | the drift of holes. |
| 2. | diffusion of charge carriers. |
| 3. | migration of impurity ions. |
| 4. | drift of electrons. |
Subtopic: Â PN junction |
 76%
From NCERT
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Subtopic: Â Applications of PN junction |
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Logic gates \(X\) and \(Y\) have the truth tables shown below:
When the output of \(X\) is connected to the input of \(Y\), the resulting combination is equivalent to a single:
1. NOT gate
2. OR gate
3. NAND gate
4. AND gate
Subtopic: Â Logic gates |
 81%
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