To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
To unlock all the explanations of 14 chapters you need to be enrolled in MasterClass Course.
The output(X) of the logic circuit shown in figure will be:
1. X =
2. X = A.B
3. X =
4. X =
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Two ideal diodes are connected to a battery as shown in the circuit. The current supplied by the battery is:
1. 0.75 A
2. zero
3. 0.25 A
4. 0.5 A
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C and Si both have the same lattice structure, having 4 bonding electrons in each. However, C is an insulator whereas Si is an intrinsic semiconductor. This is because:
1. in the case of C, the valence band is not completely filled at absolute zero temperature.
2. in the case of C, the conduction band is partly filled even at absolutely zero temperature.
3. the four bonding electrons in the case of C lie in the second orbit, whereas in the case of Si, they lie in the third.
4. the four bonding electrons in the case of C lie in the third orbit, whereas for Si, they lie in the fourth orbit.
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Transfer characteristic [output voltage () vs input voltage ()] for a base biased transistor in CE configurations as shown in the figure. For using the transistor as a switch, it is used:
1. In region III
2. Both in the region (I) and (III)
3. In region II
4. In region I
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The figure shows a logic circuit with two inputs A and B and the output C. The voltage waveforms across A, B, and C are as given. The logic circuit gate is:
1. OR gate
2. NOR gate
3. AND gate
4. NAND gate
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1. (i), (iv), and (iii)
2. (ii), (iii), and (iv)
3. (ii), (iv), and (iii)
4. (ii), (iv), and (i)
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