The symbolic representation of four logic gates 

                                       

                           (i)                                                                              (ii)

 

                                

                           (iii)                                                                              (iv)

The logic symbols for $\mathrm{OR},$ $\mathrm{NOT}$ and $\mathrm{NAND}$ gates are respectively

(a)    (iii), (iv), (ii)                                            (b)   (iv), (i), (iii)

(c)    (iv), (ii), (i)                                              (d)   (i), (iii), (iv) 

A transistor is operated in common-emitter configuration at $V_c=2volt$ such that a change in the base current from 100 $\mu A$ to 200 $\mu A$ produces a change in the collector current from 5 mA to 10 mA. The current gain is 

1. 75                                2. 100

3. 150                              4. 50

Sodium has body centred packing.Distance between two nearest atom is $3.7\stackrel{0}{A}$. The lattice parameter is 

1. 6.8 $\stackrel{0}{A}$                                     

2. 4.3 $\stackrel{0}{A}$

3. 3.0 $\stackrel{0}{A}$                                     

4. 8.6 $\stackrel{0}{A}$

If the lattice parameter for a crystalline structure is $3.6 \stackrel{0}{A},$ then the atomic radius in fcc crystal is

1. $1.81\stackrel{0}{A}$

2. $2.10\stackrel{0}{A}$

3. $2.92\stackrel{0}{A}$

4. $1.27\stackrel{0}{A}$

The voltage gain of an amplifier with 9% negative feedback is 10. The voltage gain without feedback will be

(1) 90                           

(2) 10

(3) 1.25                         

(4) 100

A p-n photodiode is made of a material with a band gap of 2.0 eV. The minimum frequency of the radiation that can be absorbed by the material is nearly

1. $10\times {10}^{14} Hz$                              2. $5\times {10}^{14} Hz$

3. $1\times {10}^{14} Hz$                                4. $20\times {10}^{14} Hz$

The circuit is equivalent to

1. AND gate                              2. NAND gate

3. NOR gate                              4. OR gate 

In the forward bias arrangement of a PN-junction diode

(1) The N-end is connected to the positive terminal of the battery

(2) The P-end is connected to the positive terminal of the battery

(3) The direction of current is from N-end to P-end in the diode

(4) The P-end is connected to the negative terminal of battery

The cut-in voltage for silicon diode is approximately

(1) 0.2 V                       

(2) 0.6 V

(3) 1.1 V                       

(4) 1.4 V